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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75P216A
4-BIT SINGLE-CHIP MICROCOMPUTER
The PD75P216A is a One-Time PROM version of the PD75216A. The PD75P216A is suitable for smallscale production or experimental production in system development. Also see documents for the PD75216A.
FEATURES
* The PD75216A compatible * 16256 ! 8 bits of on-chip one-time PROM * Port 6 without pull-down resistor * High voltage output for display S0 to S8, T0 to T9: On-chip load resistor S9, T10 to T15: Open drain * Power-on reset circuit is not available * Single power supply (5 V 10 %)
ORDERING INFORMATION
Part Number Package 64-pin plastic shrink DIP (750 mil) Quality Grade Standard
PD75P216ACW
Caution Pull-up resistor mask options are not available.
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice. Document No. IC-2670A (O.D.No. IC-7625B ) Date Published July 1993 P Printed in Japan
The mark
shows revised points.
1
(c)
NEC CORPORATION 1990 1992
PD75P216A
PIN CONFIGURATION (Top View)
S3 S2 S1 S0 P00/INT4 P01/SCK P02/SO P03/SI P10/INT0/VPP P11/INT1 P12/INT2 P13/TI0 P20 P21 P22 P23/BUZ P30/MD0 P31/MD1 P32/MD2 P33/MD3 P60 P61 P62 P63 P40 P41 P42 P43 PPO X1 X2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD S4 S5 S6 S7 S8 S9 NC VLOAD T15/S10 T14/S11 T13/S12/PH0 T12/S13/PH1 T11/S14/PH2 T10/S15/PH3 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 RESET P53 P52 P51 P50 XT2 XT1
PD75P216ACW
2
BLOCK DIAGRAM
PORT 0 BASIC INTERVAL TIMER INTBT TI0/P13 TIMER/EVENT COUNTER #0 INTT0 PORT 4 TIMER/PULSE GENERATOR INTTPG SI/P03 SO/P02 SCK/P01 SERIAL INTERFACE PROM PROGRAM MEMORY 16256 x 8BITS GENERAL REG. PROGRAM COUNTER (14) ALU CY SP (8) PORT 2 BANK PORT 1
4 4
P00-P03 P10-P13
4
P20-P23 P30/MD0- P33/MD3 P40-P43
PORT 3
4 4
PPO
PORT 5
4 4
P50-P53 P60-P63
PORT 6 DECODE AND CONTROL RAM DATA MEMORY 512 x 4BITS
10 4
T0-T9 T10/S15/PH3- T13/S12/PH0 T14/S11,T15/S10 S0-S9 VLOAD
INTSIO VPP/INT0/P10 INT1/P11 INT2/P12 INT4/P00 INTERRUPT CONTROL 10 fX/2N INTW WATCH TIMER CLOCK DIVIDER SYSTEM CLOCK GENERATOR SUB MAIN STAND BY CONTROL CPU CLOCK INTKS
FIP CONTROLLER/ DRIVER
2
PD75P216A
PORTH BUZ/P23 XT1 XT2 X1 X2 V
DD
4
PH0-PH3
VSS
RESET
3
PD75P216A
CONTENTS
1. PIN FUNCTIONS ................................................................................................................................ 5
1.1 1.2 1.3 PORT PINS .................................................................................................................................................... 5 NON-PORT PINS .......................................................................................................................................... 6 TREATMENT OF UNUSED PINS ................................................................................................................ 8
2. DIFFERENCES BETWEEN THE PD75P216A AND THE PD75216A, PD75208 ................. 9 3. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ..................................................10
3.1 3.2 3.3 PROM WRITE AND VERIFY OPERATION................................................................................................ 10 PROM WRITE PROCEDURE ...................................................................................................................... 11 PROM READ PROCEDURE ........................................................................................................................ 12
4. ELECTRICAL SPECIFICATIONS ...................................................................................................... 13 5. PACKAGE DRAWINGS .................................................................................................................... 22 6. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 23 APPENDIX DEVELOPMENT TOOLS ................................................................................................... 24
4
PD75P216A
1. PIN FUNCTIONS
1.1 PORT PINS
Input/ output Input I/O I/O Input Input Shared pin INT4 SCK SO SI INT0/VPP INT1 INT2 TI0 I/O -- -- -- BUZ I/O MD0 - MD3 Programmable 4-bit I/O port (PORT3). I/O can be specified bit by bit. 4-bit I/O port (PORT4). Can directly drive LEDs. Data input/output pins for the PROM write and verify (Four low-order bits). 4-bit I/O port (PORT5). Can directly drive LEDs. Data input/output pins for the PROM write and verify (Four high-order bits). Programmable 4-bit I/O port (PORT6). I/O can be specified bit by bit. Suitable for keyboard input. 4-bit P-ch open-drain output port Can withstand high voltage and high current (PORTH) ! ! Input E 4-bit I/O port (PORT2). ! Input E With noise elimination function With noise elimination function 4-bit input port (PORT1). ! Input 8-bit I/O ! I/O circuit type Note B F G B B
Pin name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 - P33
Function 4-bit input port (PORT0).
When reset Input
P40 - P43
I/O
--
Input
E
P50 - P53
I/O
--
Input
E
P60 - P63
I/O
--
Input
E
PH0 PH1 PH2 PH3
Output
T13/S12 T12/S13 T11/S14 T10/S15
!
High impedance
I-D
Note
The circle (
) indicates the Schmitt triggered input.
5
PD75P216A
1.2 NON-PORT PINS
Input/ output Shared pin --
Note 2
Pin name T0 - T9 T10/S15 T13/S12 T14/S11, T15/S10
Function Used for digit output Can withstand high voltage and high current For digit/segment output Can withstand high voltage and high current Unused pin can be used as PORTH.
Note 3
When reset Low level
I/O circuit type Note 1 I-E
PH3-PH0
Output
For digit/segment output Can withstand high voltage and high current Static output is possible. For segment output Can withstand high voltage Static output is possible
High impedance
I-D
S9
--
S0 -S8 PPO TI0 SCK SO SI INT4 INT0 INT1 INT2 BUZ Input I/O Output Input I/O I/O Input Input Input -- P13 P01 P02 P03 P00 P10/VPP P11 P12 P23
Note 2
For segment output Can withstand high voltage
Low level High impedance
I-E D B
Pulse output by timer/pulse generator External event pulse input to timer event counter Input and output to serial clock Serial data output or serial data input and output Serial data input or normal input Edge detection vectored interrupt input (detected at both rising edge and falling edge) Edge detection vectored interrupt input with noise elimination function (edge-detection selectable) Testable input for edge-detection (detected at rising edge) Fixed frequency output (For buzzer or system clock trimming) Crystal/ceramic resonator connection for main system clock generation. When external clock signal is used, it is applied to X1, and its reverse phase signal is applied to X2. Crystal connection for subsystem clock generation. When external clock signal is used, it is applied to XT1 and XT2 is open. System reset input (low-level active) Operation mode selection during the PROM write/verify cycles. +12.5 V is applied as the programming voltage during the PROM write/verify cycles Pull-down resistor connection of FIP controller/driver Positive power supply +6 V is applied as the programming voltage during the PROM write/verify cycles GND potential No connection
Input Input Input -- --
F G B B B
-- Input
B E
X1, X2
Input
--
--
--
XT1 XT2 RESET MD0 - MD3 VPP VLOAD
Input -- -- Input I/O -- P30 - P33 P10/INT0 --
-- -- -- -- --
-- B E B I-E
VDD VSS NC
Note 4
-- -- --
-- -- --
-- -- --
Note 1. 2. 3. 4.
The circle ( ) indicates the Schmitt triggered input. Pull-down resistor is incorporated. Open-drain output NC pin should be connected to VPRE when sharing print board with the PD75216A.
6
PD75P216A
Fig. 1-1 TYPE A
VDD
Pin Input/Output Circuit TYPE F
data Type D output disable
IN/OUT
P-ch IN
N-ch
Type B
CMOS level input buffer
I/O circuit consisting of Type D push-pull output and Type B Schmitt-triggered input
TYPE B
TYPE G
VDD P-ch output disable data
P-ch IN/OUT
IN
N-ch
Type B
Schmitt-triggered input with hysteresis
TYPE D
VDD
I/O circuit which can switch push-pull output or N-ch open-drain output (off for P-ch)
TYPE I-D
data P-ch OUT data output disable N-ch N-ch OUT
Push-pull output which can be set to high-impedance output (off for both P-ch and N-ch)
VDD
VDD
P-ch
P-ch
TYPE E
TYPE I-E
VDD IN/OUT Type D data P-ch P-ch OUT VDD
data output disable
N-ch Type A
Pull-down resistor VLOAD
I/O circuit consisting of Type D push-pull output and Type A input buffer.
7
PD75P216A
1.3 TREATMENT OF UNUSED PINS Table 1-2 Recommended Connection for Unused Pins Pin P00/INT4 P01/SCK P02/SO P03/SI P10/INT0/VPP P11/INT1, P12/INT2 P13/T10 P20 - P22 P23/BUZ P30/MD0 - P33/MD3 P40 - P43 P50 - P53 P60 - P63 PPO S0 - S9 T15/S10, T14/S11 T0 - T9 T10/S15/PH3-T13/S12/PH0 XT1 XT2 Connect to VSS or VDD Open Open Input: Connect to VSS or VDD Output: Open Connect to VSS Connect to VSS or VDD Recommended connection Connect to VSS
8
PD75P216A
2. DIFFERENCES BETWEEN THE PD75P216A AND THE PD75216A, PD75208
Table 2-1
Parameter
Differences between the PD75P216A and the PD75216A, PD75208
PD75P216A
One-time PROM
PD75216A
PD75208
Mask ROM 8064 x 8 bits (0000H - 1F7FH) 497 x 4 bits 9 - 12 segments
ROM
16256 x 8 bits (0000H - 3F7FH) 512 x 4 bits 9 - 16 segments N/A On-chip N/A (Open-drain) N/A
RAM FIP
(R)
Controller Driver Port 6
Pull-Down Registor
S0 - S8, T0 - T9 S9, T10 - T15
Mask option
Power-On Reset Mask option P10/INT0 P30 - P33 VPRE -40 to +85 C 2.7 to 6.0 V 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP (14 x 20 mm) Power-On Flag P10/INT0/VPP Pin Connection P30/MD0 - P33/MD3 NC Operating Ambient Temperature Operating Supply Voltage Package -10 to +70 C 5 V 10 % 64-pin plastic shrink DIP (750 mil)
9
PD75P216A
3. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY
The PD75P216A contains 16256 x 8 bits of one-time PROM available of writing. The following table shows the pin functions during the write and verify cycles. Note that it is not necessary to enter an address, because the address is updated by pulsing the X1 clock pins. Table 3-1
Pin name VPP
Used Pin at PROM Write and Verify
Function Voltage application pin for write and verify (Normally VDD potential) Address-update clock input during write/verify. The inverted signal of the X1 should be input to the X2. Operation mode selection pins for write and verify 8-bit data input/output pins for write and verify
X1, X2
MD0 - MD3 P40 - P43 (lower 4 bits) P50 - P53 (higher 4 bits) VDD
Supply voltage application pin Normally 5 V 10 %; 6 V is applied during write/verify
Caution 1.
The pins which are not used during write or verify should be treated as follows * Port, XT1, RESET ... Connect to VSS through pull-down resistors * S0 to S9, T0 to T15, PPO, VLOAD ... Connect to VDD through pull-up resistors * XT2 ... Open
2.
The PD75P216A do not have a UV erase window, thus the PROM contents cannot be erased with ultra violet ray.
3.1
PROM WRITE AND VERIFY OPERATION
When +6 V and +12.5 V are applied to the VDD and VPP pins, respectively, the PROM is placed in the write/ verify mode. The operation is selected by the MD0 to MD3 pins, as shown in the table. Table 3-2 PROM Write and Verify Operation
Operation mode specification Operation mode VPP +12.5 VDD +6 V MD0 H L L H x: Don't care. MD1 L H L x MD2 H H H H MD3 L H H H Clear program memory address to 0 Write mode Verify mode Program inhibit mode
10
PD75P216A
3.2 (1) (2) (3) (4) (5) (6) (7) (8) (9) PROM WRITE PROCEDURE Pull unused pins to VSS through resistors. Set the X1 pin low. Supply 5 volts to the VDD and VPP pins. Wait for 10 s. Select the zero clear program memory address mode. Supply 6 volts to the VDD and 12.5 volts to the VPP pins. Select the program inhibit mode. Write data in the 1 ms write mode. Select the program inhibit mode. Select the verify mode. If the data is correct, proceed to step (10). If not repeat steps (7), (8) and (9).
PROM can be written at high speed using the following procedure: (see the following figure)
(10) Perform one additional write (duration of 1ms x number of writes at (7) to (9)). (11) Select the program inhibit mode. (12) Apply four pulses to the X1 pin to increment the program memory address by one. (13) Repeat steps (7) to (12) until the end address is reached. (14) Select the zero clear program memory address mode. (15) Return the VDD and VPP pins back to + 5 volts. (16) Turn off the power. Fig. 3-1 Timing of Program Memory Write
X repetition Write Verify Additional write Address increment
VPP VPP VDD VDD+1 VDD VDD X1
P40-P43 P50-P53
Input data
Output data
Input data
MD0 (P30)
MD1 (P31)
MD2 (P32)
MD3 (P33)
11
PD75P216A
3.3 PROM READ PROCEDURE
The PROM contents can be read in the verify mode by using the following procedure: (see the following figure) (1) (2) (3) (4) (5) (6) (7) (8) (9) Pull unused pins to VSS through resistors. Set the X1 pin low. Supply 5 volts to the VDD and VPP pins. Wait for 10 s. Select the zero clear program memory address mode. Supply 6 volts to the VDD and 12.5 volts to the VPP pins. Select the program inhibit mode. Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored in one address. Select the program inhibit mode. Select the zero clear program memory address mode.
(10) Return the VDD and VPP pins back to + 5 volts. (11) Turn off the power. Fig. 3-2 Timing of Program Memory Read
VPP VPP VDD
VDD+1 VDD VDD
X1
P40-P43 P50-P53
Output data
Output data
MD0 (P30)
MD1 (P31)
"L"
MD2 (P32)
MD3 (P33)
12
PD75P216A
4. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (Ta = 25 C)
Parameter Symbol VDD Supply voltage VLOAD VPP Input voltage Output voltage VI VO VOD Other than display pins Display pins
Single pin; other than display pins
Conditions
Ratings -0.3 to +7.0 VDD -40 to VDD + 0.3 -0.3 to +13.5 -0.3 to VDD +0.3 -0.3 to VDD +0.3 VDD -40 to VDD + 0.3 -15 -15 -30 -20 -120 17 60 -10 to +70 -65 to +150
Unit V V V V V V mA mA mA mA mA mA mA C C
Single pin; S0 - S9 High-level output current IOH Single pin; T0 - T15
Total of all pins other than diplay
Total of all display pins Single pin Low level output current Operating temperature Storage temperature IOL Total of all pins Topt Tstg
Operating Supply Voltage (Ta = -10 to + 70 C)
Parameter CPU
Note
Conditions
MIN. 4.5 4.5 4.5 4.5
MAX. 5.5 5.5 5.5 5.5
Unit V V V V
Display controller Timer/pulse generator Other hardwares
Note
Note
Except system clock oscillation circuit, display controller, timer/pulse generator.
13
PD75P216A
Main System Clock Configurations (Ta = -10 to +70 C, VDD = 5 V 10 %)
Resonator Recommended constants Parameter
Note 1
Conditions VDD = Oscillator operating voltage range After VDD reaches the minimum oscillator operating voltage range
MIN.
TYP.
MAX.
Unit
X1
X2
Oscillation frequency (fXX)
Note 2
2.0
5.0
Note 3
MHz
Ceramic resonator
C1 C2
Oscillation stabilization time
4
ms
Note 1
X1
Crystal resonator
X2
Oscillation frequency (fXX)
Note 2
2.0
4.19
5.0
Note 3
MHz
C1
C2
Oscillation stabilization time
10
ms
Note 1
X1
X2
X1 input frequency (fX) X1 input high- and low-level width (tXH, tXL)
2.0
5.0
Note 3
MHz
External clock
PD74HCU04
100
250
ns
Subsystem Clock Configurations (Ta = -10 to +70 C, VDD = 5 V 10 %)
Resonator Recommended constants Parameter
Note 1
Conditions
MIN.
TYP.
MAX.
Unit
XT1
Crystal resonator
XT2 R
Oscillation frequency (fXT)
Note 2
32
32.768
35
kHz
C3
C4
Oscillation stabilization time
1
2
s
XT1
External clock
XT2 Open
XT1 input frequency (fXT)
32
100
kHz
X1 input high- and low-level width (tXTH, tXTL)
10
32
s
Note 1. The oscillation frequency and input frequency only indicate the characteristics of the oscillation circuit. Refer to the AC characteristics for the instruction execution time. 2. The oscillation stabilization time is the time until the oscillation enters a stable state after the application of VDD or the release of STOP mode. 3. When the oscillation frequency is 4.19 < fX 5.0 MHz, PCC = 0011 should not be selected as the instruction execution time. If PCC = 0011 is selected, 1 machine cycle is less than the specified minimum value, which is 0.95 s.
14
PD75P216A
Capacitance (Ta = 25 C, VDD = 0 V)
Parameter Input capacitance Other than display output Output capacitance Display output Input/Output capacitance CIO COUT Symbol CIN Conditions MIN. TYP. MAX. 15 15 f = 1 MHz Unmeasured pins returned to 0 V 35 15 pF pF Unit pF pF
DC Characteristics (Ta = -10 to +70 C, VDD = 5 V 10 %)
Parameter Symbol VIH1 High-level input voltage VIH2 VIH3 VIH4 VIL1 Low-level input voltage VIL2 VIL3 High-level output voltage VOH Conditions All except ports 0, 1, 6, X1, X2, XT1, RESET Port 0, 1 RESET X1, X2, XT1 Port 6 All except ports 0, 1, 6, X1, X2, XT1, RESET Port 0, 1, 6 RESET X1, X2, XT1 IOH = -1 mA All outputs Port 4, 5 Low-level output voltage High-level input leakage current Low-level input leakage current High-level output leakage current Low-level output leakage current VOL ILIH1 ILIH2 ILIL1 ILIL2 ILOH ILOL1 ILOL2 IOD T0 - T15 On-chip pull-down resistor RL IDD1 IDD2 Power supply current
Note 1
MIN. 0.7 VDD 0.75 VDD VDD-0.4 0.65 VDD 0 0 0 VDD-1.0 VDD-0.5
TYP.
MAX. VDD VDD VDD VDD 0.3 VDD 0.2 VDD 0.4
Unit V V V V V V V V V
IOH = -100 A IOL = 15 mA IOL = 1.6 mA VI = VDD
0.4
2.0 0.4 3 20 -3
V V
All outputs All except X1, X2, XT1 X1, X2, XT1 All except X1, X2, XT1 X1, X2, XT1 All outputs All except display output Display outputs S0 - S9
A A A A A A A
mA mA
VI = 0 V
-20 3 -3 -10 -3 -5.5 -22 70 3.0 600 100 135 9.0 1 800 300 100 20
VO = VDD VO = 0 V VO = VLOAD = VDD - 35 V VOD = VDD - 2 V -15 VOD - VLOAD = 35 V
Note 2
Display output current
Display outputs 4.19 MHz Crystal oscillator C1 = C2 = 15 pF 32.768 kHz Crystal oscillator XT1 = 0 V
Note 3
25
k mA
HALT mode
A A A A
IDD3 IDD4 IDD5
HALT mode STOP mode
40 0.5
Note 1. Does not include the current for the on-chip pull-down resistor (output circuit to S0 to S8, T0 to T9). 2. When the processor clock control register (PCC) is set to 0011 and operated in high-speed mode. 3. When the system clock control register (SCC) is set to 1001 to stop the main system clock, and when the sub-system clock is used.
15
PD75P216A
AC Characteristics (Ta = -10 to +70 C, VDD = +5 V 10%)
Parameter CPU clock time (minimum instruction execution time = 1 machine cycle) TI0 input frequency
Note 1
Symbol tCY
Conditions Main system clock Subsystem clock
MIN. 0.95 114 0 0.83 Input 0.8 0.95 0.4 tKCY/2-50 100 400
TYP.
MAX. 32
Unit
s s
MHz
122
125 0.6
fTI
TI0 input high- and low-level width tTIH, tTIL SCK cycle time tKCY Output Input SCK high- and low-level width SI setup time (to SCK ) SI hold time (to SCK ) SCK SO output delay time Interrupt inputs high- and low-level width tKH, tKL Output tSIK tKSI tKSO INT0 tINTH, tINTL INT1 INT2, 4 RESET low-level width tRSL
s
s
s s
ns ns ns 300 ns
Note 2
s
2tCY 10 10
s
s s
Note 1. The CPU clock (o) cycle time is decided by the oscillation frequency of the resonator, system clock control register (SCC), and processor clock control register (PCC). The figure to the right indicates cycle time (tCY) characteristics for supply voltage VDD when using the main system clock. 2. This is 2tCY or 128/fXX according to the interrupt mode register setting (IM0).
tCY vs VDD (Main system clock)
50
Guaranteed operating range
Cycle time tCY [ s]
10
5
1
0.5 0 1 2 3 4 5 6
Power supply voltage VDD [V]
16
PD75P216A
AC timing Test Point (Except X1, XT1)
0.75 VDD 0.2 VDD
Test points
0.75 VDD 0.2 VDD
Clock Timing
1/fX tXL tXH
X1 input
VDD - 0.4 V 0.4 V
1/fXT tXTL tXTH
XT1 input
VDD - 0.4 V 0.4 V
TIO Timing
1/fTI tTIL tTIH
TIO
17
PD75P216A
Serial Transfer Timing
tKCY tKL tKH
SCK
tSIK
tKSI
SI
Input data
tKSO
SO
Output data
Interrupt Input Timing
tINTL
tINTH
INT0, 1, 2, 4
RESET Input Timing
tRSL
RESET
18
PD75P216A
Data Memory STOP Mode Low Voltage Data Retention Characteristics (Ta = -10 to +70 C)
Parameter Data retention voltage Data retention current Released signal SET time
Note 1
Symbol VDDDR IDDDR tSREL VDDDR = 2.0 V
Conditions
MIN. 2.0
TYP.
MAX. 5.5
Unit V
0.1 0
10
A s
Released by RESET input tWAIT Released by interrupt request
217/fX
Note 2
ms ms
Oscillation stabilization time
Note 1. The oscillation stabilization wait time is a period during which the CPU is kept inactive in order to avoid unstable operation at the start of oscillation. 2. Depends on the setting of the basic interval time mode register (BTM) (see the following table).
BTM3 -- -- -- -- BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1
20
Wait time ( 2 /fXX (approx. 250 ms) 217/fXX (approx. 31.3 ms) 215/fXX (approx. 7.82 ms) 213/fXX (approx. 1.95 ms)
): fXX = 4.19 MHz
Data Retention Timing (STOP mode is released by RESET input)
Internal reset operation HALT mode STOP mode Data retention mode Operation mode
VDD VDDDR Execution of STOP instruction tSREL
RESET tWAIT
Data Retention Timing (Standby release signal: STOP mode is released by interrupt signal)
HALT mode STOP mode Data retention mode Operation mode
VDD
VDDDR Execution of STOP instruction
tSREL
Standby release signal (interrupt request) tWAIT
19
PD75P216A
DC Programming Characteristics (Ta = 25 5 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
Parameter High-level input voltage Symbol VIH1 VIH2 VIL1 VIL2 IL1 VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Conditions All except X1, X2 X1, X2 All except X1, X2 X1, X2 VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA VDD-1.0 0.4 30 30 MIN. 0.7 VDD VDD-0.5 0 0 TYP. MAX. VDD VDD 0.3 VDD 0.4 10 Unit V V V V
Low-level input voltage Input leakage current High-level output voltage Low-level output voltage VDD power supply current VPP power supply current
A
V V mA mA
Note 1. VPP should not exceed +22 V (including overshoot). 2. VDD should be applied before VPP and turned off after VPP. AC Programming Characteristics (Ta = 25 5 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
Parameter Address setup time MD1 setup time Data setup time Address hold time Data hold time
Note 2 Note 2
Symbol Note 1 (toMD0) (to MD0) (to MD0) (from MD0) tAS tMIS tDS tAH tDH tDF tVPS tVDS tPW tOPW tMOS tDV tMIH tMIR tPCR tXH, tXL fX tI (to MD1) tM3S tM3H tM3SR tDAD tHAD tM3HR tDFR tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR -- -- -- -- -- -- -- tACC tOH -- --
Conditions
MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2
TYP.
MAX.
Unit
s s s s s
130 ns
(from MD0)
MD0 data output float delay time
VPP setup time VDD setup time
(to MD3) (to MD3)
s s
1.0 1.05 21.0 ms ms
Initialized program pulse width Additional program pulse width MD0 setup time (to MD1) MD0 data output delay time MD1 hold time MD1 recovery time (from MD0) (to MD0)
s
1
MD0 = MD1 = VIL tMIH + tMIR 50 s 2 2 10 0.125
s s s s s
Program counter reset time
X1 input high- and low-level width
X1 input frequency Initial mode set time MD3 setup time MD3 hold time MD3 setup time
Address
Note 2
4.19 2 2 2 During program read cycle During program read cycle During program resd cycle During program read cycle During program read cycle 2 2 0 2 2 130
MHz
s s s s s
ns
(from MD1) (to MD0)
Data output delay time
Address Note 2 Data output hold time MD3 hold time (from MD0)
MD3 data output float delay time
s s
Note 1. Symbol of corresponding PD27C256. 2. Internal address is incremented by 1 at the rising edge of the fourth X1 input. This address signal is not output to external pins.
20
PD75P216A
Program Memory Write Timing
tVPS
VPP VPP VDD
tVDS VDD+1 VDD VDD X1 tXL Input data tI MD0 tPW MD1 tPCR MD2 tM3S MD3 tM1S tM1H tM3H tM1R tMOS tOPW tDS tOH tDV tDF
Output data
tXH
P40-P43 P50-P53
Input data tDS tDH tAH tAS
Input data
Program Memory Read Timing
tVPS VPP VPP VDD tVDS VDD+1 VDD VDD
tXH
X1 tXL tHAD P40-P43 P50-P53 tI MD0 tDV tM3HR Output data Output data tDFR tDAD
MD1 tPCR MD2 tM3SR MD3
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PD75P216A
5. PACKAGE DRAWINGS
64 PIN PLASTIC SHRINK DIP (750 mil)
64 33
1 A
32
K L
J I
F D
G
H
N
M
C
B
M
R
NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM MILLIMETERS A B C D F G H I J K L M N R 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 -0.003 0.007 0~15 P64C-70-750A,C-1
22
PD75P216A
6. RECOMMENDED SOLDERING CONDITIONS
The following conditions must be met when soldering this product. For more details, refer to our document "SEMICONDUCTOR MANUAL" (IEI-1207). Please consult with our sales offices in case other soldering process is used, or in case other soldering is done under different conditions. Table 6-1 Type of Through Hole Device DEVICE MOUNTING TECHNOLOGY
PD75P216ACW: 64-pin plastic shrink DIP (750 mil)
Soldering process Wave soldering (only lead part) Partial heating method Soldering conditions Solder temperature: 260 C or lower, Flow time: 10 seconds or less Pin temperature: 260 C or lower, Time: 10 seconds or less
Caution This wave soldering should be applied only to lead part, and don't jet molten solder on the surface of package.
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PD75P216A
APPENDIX DEVELOPMENT TOOLS
The following development tools are provided for the development of a system which employs the
PD75P216A.
Language processor
RA75X relocatable assembler Host machine OS PC-9800 series MS-DOSTM Ver. 3.10 to Ver. 3.30C PC DOSTM (Ver. 3.1) Distribution media 3.5-inch 2HD Part number
S5A13RA75X S5A10RA75X S7B10RA75X
5-inch 2HD 5-inch 2HC
IBM PC series
PROM programming tools
Hardware PG-1500 The PG-1500 PROM programmer is used together with an accessory board and optional programmer adapter. It allows the user to program a single chip microcomputer containing PROM from a standalone terminal or a host machine. The PG-1500 can be used to program typical 256K-bit to 4M-bit PROMs. PROM programmer adapter dedicated to PD75P216ACW. Connect the programmer adapter to PG-1500 for use. PROM programmer produced by Ando Electric Corp. Programmer adapter dedicated to the PD75P216ACW Connect to AF-9703, AF-9704 for use PROM programmer produced by Data I/O Japan Corp.
PA-75P216ACW
AF-9703 AF-9704 AF-9789
UNISITE 2900 3900 PPI-0601
Programmer adapter dedicated to the PD75P216ACW Connect to UNISITE, 2900, 3900 for use This program enables the host machine to control the PG-1500 through the serial and parallel interfaces. Host machine OS PC-9800 series MS-DOS Ver. 3.10 to Ver. 3.30C PC DOS (Ver. 3.1) Distribution media 3.5-inch 2HD 5-inch 2HD 5-inch 2HC Part number
Software
PG-1500 controller
S5A13PG1500 S5A10PG1500 S7B10PG1500
IBM PC series
24
PD75P216A
Debugging tools
Hardware IE-75000-R
Note
The IE-75000-R is an in-circuit emulator to debug the hardware and software at developing application system for 75X series. This emulator is used together with the emulation probe. For efficient debugging, the emulator is connected to the host machine and PROM programmer. The IE-75000-R-EM is an emulation board for the IE-75000-R and IE-75001-R. The IE-75000-R contains the emulation board. The emulation board is used together with the IE-75000-R or IE-75001-R to evaluate the PD75P048. The IE-75001-R is an in-circuit emulator to debug the hardware and software at developing application system for 75X series. This emulator is used together with the IE-75000-R-EM emulation board (option) and emulation probe. For efficient debugging, the emulator is connected to the host machine and PROM programmer. Emulation probe for the PD75P216ACW. Connect this probe to the IE-75000-R or IE-75001-R and the IE-75000-R-EM for use. This program enables the host machine to control the IE-75000-R or IE-75001-R on the host machine through the RS-232-C interface. Host machine OS PC-9800 series MS-DOS Ver. 3.10 to Ver. 3.30C PC DOS (Ver. 3.1) Distribution media 3.5-inch 2HD 5-inch 2HD 5-inch 2HC Part number
IE-75000-R-EM
IE-75001-R
EP-75216ACW-R
Software
IE control program
S5A13IE75X S5A10IE75X S7B10IE75X
IBM PC series
Notes
Provided only for maintenance purposes.
Remark NEC is not responsible for the IE control program operation unless it runs on any host machine with the operation system listed above.
25
26
Configuration of Development Tools
In-circuit emulator Emulation probe Centronics interface IE-75000-R IE-75001-R Note 1 RS-232-C Host machine IE control program IE-75000-R-EM
Note 2
EP-75216ACW-R EP-75216AGF-R
User system
PG-1500 PC-9800 series controller IBM PC series (Symbol debugging possible) PROM programmer PG-1500
PROM version
PD75P216ACW
Relocatable assembler
Programmer adapter PA-75P216ACW
Notes 1. IE-75001-R is not provided with IE-75000-R-EM (option) 2. EV-9200GC-64
PD75P216A
PD75P216A
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pullup or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
STATUS BEFORE INITIAIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
27
PD75P216A
"PD75216A USER'S MANUAL" (IEM-988F) is also prepared for this product (option).
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
M4 92.6
(R) FIP is a trademark of NEC Corporation. MS-DOS TM is a trademark of Microsoft Corporation. PC DOS TM is a trademark of IBM Corporation.
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